1. Field of the Invention
The present invention relates to a signature compression circuit that latches test outputs from an object to be tested, compresses them in parallel and provides a signature (resultant data) of the test at the end of the test and reads the signature by scanning. Particularly, the invention is effective for simplifying the design of test circuits.
2. Description of the Prior Art
One method employed to analyze high speed integrated circuits is a parallel signature compression method. This method will be explained with reference to FIG. 1. In this figure, a combination circuit 1 is tested. A test input pattern is given to the combination circuit 1, which provides test outputs to an output register 3. The test outputs are compressed in the output register 3 in parallel. At the end of the test, a signature (resultant data) of the test is stored in the register 3. Analysis of the combination circuit 1 according to the parallel signature compression method will be explained in more detail.
The test outputs of the combination circuit 1 are fetched by the output register 3. The output register 3 operates as a linear feedback shift register (LFSR) with parallel inputs, and the test outputs of the combination circuit 1 are compressed in parallel in the output register 3.
A signature (resultant data) of the test which is generated by compressing the test outputs of the combination circuit 1 is read out of the output register 3 by scanning and transferring. Then, the externally read contents are compared with expected values. Based on the comparison, the combination circuit 1 is analyzed.
In this way, the output register 3 will latch the test outputs, compress them in parallel and carry out the scanning operation. To do so, the output register 3 is provided with hardware for realizing such operations.
FIG. 2 shows a conventional signature compression circuit comprising an output register provided with such hardware for executing the parallel signature compression. The circuit of FIG. 2 is based on a built-in logic block observer (BILBO) system.
In this figure, test outputs of a combination circuit to be tested are eight bits (Z1 to Z8), and the output register comprises flip-flop circuits (hereinafter referred to as F/Fs) 5 corresponding to the eight bits of the test outputs, respectively. Each F/F 5 is connected to the next F/F 5 on the upper bit side via a negative OR (NOR) gate 7 and an exclusive OR (EXOR) gate 9. Each F/F 5 receives corresponding one of the test outputs via an AND gate 11 and the EXOR gate 9. One input of each AND gate 11 receives a control signal A, and one input of each NOR gate 7 receives a control signal B. These control signals A and B control the outputs of the gates 7 and 11.
When the control signal A is at a level of "1", the gates 11 are enabled so that the test outputs Zn are latched in the output register which may form a linear feedback shift register (LFSR). When the control signal B is at a level of "1", the gates 7 are disabled so that the F/Fs 5 will be independent of each other. In this way, the control signals A and B determine the function of the output register as a whole.
To compress the test outputs in parallel, the conventional signature compression circuit based on the BILBO system will have gate circuits such as the EXOR gates 9 and AND gates 11 inserted between the outputs of a circuit to be tested and the output register comprising the F/Fs 5.
Therefore, if the number of outputs of the circuit to be tested is large, the number of the gate circuits should be increased, i.e., areas occupied by the gate circuits in an integrated circuit should be increased, thus increasing the size of the integrated circuit.
Since the test outputs are provided to the F/Fs via the two stages of gate circuits, there are delays caused by the two stages of gate circuits. If high speed specifications are to be observed, it is hard to employ such conventional signature compression circuits, or, if employed, the specifications need to be loosened.